Khushboo Gupta

Student at Bharati vidyapeeth college of engineering for women

Rate of Change

problems on Rate of Change

80386

80386 - Features Architecture of 80386 Registers Instruction Pointer Addressing Modes Programming Model

INTRODUCTION TO 8051 MICROCONTROLLER

INTRODUCTION TO 8051 MICROCONTROLLER Advantages Uses of Microcontrollers Features of 8051 Block Diagram Pin Diagram Pins of 8051 Memory Spaces Internal ROM I/O Ports Register Set Program Status Word Stack and Stack Pointer Data Pointer Memory Organization Ports and Circuits External Program Memory Timing Waveforms Interrupt Vector locations Instructions to access external ROM/ Program Memory 8051 Data Memory Instructions to access external data memory Serial Ports SCON PCON Operating Modes for Serial Port Interrupts Addressing Modes

MULTITASKING

MULTITASKING Input/Output Task Gate Descriptor

Interrupts and Exceptions

Interrupts Exceptions Interrupt / Exception Processing Interrupt vectoring for procedures Processing ISRs Returning from Interrupt Procedures

UNIT – II 80386 MEMORY MANAGEMENT

Pin Description Features of Protected Mode Protected Mode Registers Addressing Mechanism Segment Descriptor System Segment Descriptor Gate Descriptors Descriptor Tables GDTR and GDT IDTR and IDT GDT and IDT Segment Registers Linear Address Format Protection Limit Checking Privilege Level Resticting Access to Data

Digital Signals Processing manuals

Digital Signals Processing manuals of PUNE UNIVERSITY

Combinational Logic Circuit

*Basic of Digital Electronics *SOP and POS *Representation of Gates *K-Map *Grouping in MAP *Don't Care Condition *Combinational Logic Design *Code converter *Parallel Adder using logic gates *Lock ahead Carry Generator *Comparator *Multiplexer *Parity Generator and Checker

Analog Circuit

SECTION 8.1: INTRODUCTION 8.1 SECTION 8.2: THE TRANSFER FUNCTION 8.5 THE S-PLANE 8.5 FO and Q 8.7 HIGH-PASS FILTER 8.8 BAND-PASS FILTER 8.9 BAND-REJECT (NOTCH) FILTER 8.10 ALL-PASS FILTER 8.12 PHASE RESPONSE 8.14 THE EFFECT OF NONLINEAR PHASE 8.16 SECTION 8.3: TIME DOMAIN RESPONSE 8.19 IMPULSE RESPONSE 8.19 STEP RESPONSE 8.20 SECTION 8.4: STANDARD RESPONSES 8.21 BUTTERWORTH 8.21 CHEBYSHEV 8.21 BESSEL 8.23 LINEAR PHASE with EQUIRIPPLE ERROR 8.24 TRANSITIONAL FILTERS 8.24 COMPARISON OF ALL-POLE RESPONSES 8.25 ELLIPTICAL 8.26 MAXIMALLY FLAT DELAY with CHEBYSHEV STOP BAND 8.27 INVERSE CHEBYSHEV 8.27 USING THE PROTOTYPE RESPONSE CURVES 8.29 RESPONSE CURVES BUTTERWORTH RESPONSE 8.31 0.01 dB CHEBYSHEV RESPONSE 8.32 0.1 dB CHEBYSHEV RESPONSE 8.33 0.25 dB CHEBYSHEV RESPONSE 8.34 0.5 dB CHEBYSHEV RESPONSE 8.35 1 dB CHEBYSHEV RESPONSE 8.36 BESSEL RESPONSE 8.27 LINEAR PHASE with EQUIRIPPLE ERROR of 0.05° RESPONSE 8.38 LINEAR PHASE with EQUIRIPPLE ERROR of 0.5° RESPONSE 8.39 GAUSSIAN TO 12 dB RESPONSE 8.40 GAUSSIAN TO 6 dB RESPONSEBASIC LINEAR DESIGN SECTION 8.4: STANDARD RESPONSES (cont.) DESIGN TABLES BUTTERWORTH DESIGN TABLE 8.42 0.01 dB CHEBYSHEV DESIGN TABLE 8.43 0.1 dB CHEBYSHEV DESIGN TABLE 8.44 0.25 dB CHEBYSHEV DESIGN TABLE 8.45 0.5 dB CHEBYSHEV DESIGN TABLE 8.46 1 dB CHEBYSHEV DESIGN TABLE 8.47 BESSEL DESIGN TABLE 8.48 LINEAR PHASE with EQUIRIPPLE ERROR of 0.05° DESIGN TABLE 8.49 LINEAR PHASE with EQUIRIPPLE ERROR of 0.5° DESIGN TABLE 8.50 GAUSSIAN TO 12 dB DESIGN TABLE 8.51 GAUSSIAN TO 6 dB DESIGN TABLE 8.52 SECTION 8.5: FREQUENCY TRANSFORMATION 8.55 LOW-PASS TO HIGH-PASS 8.55 LOW-PASS TO BAND-PASS 8.56 LOW-PASS TO BAND-REJECT (NOTCH) 8.59 LOW-PASS TO ALL-PASS 8.61 SECTION 8.6: FILTER REALIZATIONS 8.63 SINGLE POLE RC 8.64 PASSIVE LC SECTION 8.65 INTEGRATOR 8.67 GENERAL IMPEDANCE CONVERTER 8.68 ACTIVE INDUCTOR 8.69 FREQUENCY DEPENDENT NEGATIVE RESISTOR (FDNR) 8.70 SALLEN-KEY 8.72 MULTIPLE FEEDBACK 8.75 STATE VARIABLE 8.77 BIQUADRATIC (BIQUAD) 8.79 DUAL AMPLIFIER BAND-PASS (DABP) 8.80 TWIN T NOTCH 8.81 BAINTER NOTCH 8.82 BOCTOR NOTCH 8.83 1 BAND-PASS NOTCH 8.85 FIRST ORDER ALL-PASS 8.86 SECOND ORDER ALL-PASS 8.87 SECTION 8.6: FILTER REALIZATIONS (cont.) DESIGN PAGES SINGLE-POLE 8.88 SALLEN-KEY LOW-PASS 8.89 SALLEN-KEY HIGH-PASS 8.90 SALLEN-KEY BAND-PASS 8.91 MULTIPLE FEEDBACK LOW-PASS 8.92 MULTIPLE FEEDBACK HIGH-PASS 8.93 MULTIPLE FEEDBACK BAND-PASS 8.94 STATE VARIABLE 8.95 BIQUAD 8.98 DUAL AMPLIFIER BAND-PASS 8.100 TWIN T NOTCH 8.101 BAINTER NOTCH 8.102 BOCTOR NOTCH (LOW-PASS) 8.103 BOCTOR NOTCH (HIGH-PASS) 8.104 FIRST ORDER ALL-PASS 8.106 SECOND ORDER ALL-PASS 8.107 SECTION 8.7: PRACTICAL PROBLEMS IN FILTER IMPLEMENTATION 8.109 PASSIVE COMPONENTS 8.109 LIMITATIONS OF ACTIVE ELEMENTS (OP AMPS) IN FILTERS 8.114 DISTORTION RESULTING FROM INPUT CAPACITANCE MODULATION 8.115 Q PEAKING AND Q ENHANSEMENT 8.117 SECTION 8.8: DESIGN EXAMPLES 8.121 ANTIALIASING FILTER 8.121 TRANSFORMATIONS 8.128 CD RECONSTRUCTION FILTER 8.134 DIGITALLY PROGRAMMABLE STATE VARIABLE FILTER 8.137 60 HZ. NOTCH FILTER 8.141 REFERENCES 8.14

OP AMP

INTRODUCTION 1.1 SECTION 1.1: OP AMP OPERATION 1.3 INTRODUCTION 1.3 VOLTAGE FEEDBACK (VFB) MODEL 1.3 BASIC OPERATION 1.4 INVERTING AND NONINVERTING CONFIGURATIONS 1.5 OPEN-LOOP GAIN 1.9 GAIN BANDWIDTH PRODUCT 1.11 STABILITY CRITERIA 1.11 PHASE MARGIN 1.13 CLOSED-LOOP GAIN 1.13 SIGNAL GAIN 1.14 NOISE GAIN 1.14 LOOP GAIN 1.15 BODE PLOT 1.16 CURRENT FEEDBACK (CFB) MODEL 1.17 DIFFERENCES FROM VFB 1.17 HOW TO CHOOSE BETWEEN VFB AND CFB 1.19 SUPPLY VOLTAGES 1.19 SINGLE-SUPPLY CONSIDERATIONS 1.20 CIRCUIT DESIGN CONSIDERATIONS FOR SINGLE- SUPPLY SYSTEMS 1.23 RAIL-TO-RAIL 1.25 PHASE REVERSAL 1.25 LOW POWER AND MICROPOWER 1.25 PROCESSES 1.26 EFFECTS OF OVERDRIVE ON OP AMP INPUTS 1.27 SECTION 1.2: OP AMP SPECIFICATIONS 1.29 INTRODUCTION 1.29 DC SPECIFICATIONS 1.30 OPEN-LOOP GAIN 1.30 OPEN-LOOP TRANSRESISTANCE OF A CFB OP AMP 1.32 OFFSET VOLTAGE 1.33 OFFSET VOLTAGE DRIFT 1.33 DRIFT WITH TIME 1.33 SECTION 1.2: OP AMP SPECIFICATIONS (cont.) CORRECTION FOR OFFSET VOLTAGE 1.34 DigiTrim™ TECHNOLOGY 1.34 EXTERNAL TRIM 1.36 INPUT BIAS CURRENT 1.38 INPUT OFFSET CURRENT 1.38 COMPENSATING FOR BIAS CURRENT 1.39 CALCULATING TOTAL OUTPUT OFFSET ERROR DUE TO IB AND VOS 1.41 BASIC LINEAR DESIGN INPUT IMPEDANCE 1.42 INPUT CAPACITANCE 1.43 INPUT COMMON MODE VOLTAGE RANGE 1.43 DIFFERENTIAL INPUT VOLTAGE 1.44 SUPPLY VOLTAGES 1.44 QUIESCENT CURRENT 1.44 OUTPUT VOLTAGE SWING (OUTPUT VOLTAGE HIGH / OUTPUT VOLTAGE LOW) 1.45 OUTPUT CURRENT (SHORT-CIRCUIT CURRENT) 1.45 AC SPECIFICATIONS 1.47 NOISE 1.47 VOLTAGE NOISE 1.47 NOISE BANDWIDTH 1.48 NOISE FIGURE 1.48 CURRENT NOISE 1.49 TOTAL NOISE (SUM OF NOISE SOURCES) 1.49 1/f NOISE (FLICKER NOISE) 1.51 POPCORN NOISE 1.52 RMS NOISE CONSIDERATIONS 1.53 TOTAL OUTPUT NOISE CALCULATIONS 1.55 DISTORTION 1.60 THD (TOTAL HARMONIC DISTORTION) 1.60 THD + N (TOTAL HARMONIC DISTORTION PLUS NOISE) 1.60 INTERMODULATION DISTORTION 1.61 THIRD+C65 ORDER INTERCEPT POINT (IP3), SECOND ORDER C56 INTERCEPT POINT (IP2) 1.61 1 dB COMPRESSION POINT 1.63 SNR (SIGNAL TO NOISE RATIO) 1.63 ENOB (EQUIVALENT NUMBER OF BITS) 1.63 OP AMP SPECIFICATIONS (cont.) SPURIOUS-FREE DYNAMIC RANGE (SFDR) 1.64 SLEW RATE 1.64 FULL POWER BANDWIDTH 1.65 −3 dB SMALL SIGNAL BANDWIDTH 1.66 BANDWIDTH FOR 0.1 dB BANDWIDTH FLATNESS+C65 1.66 GAIN-BANDWIDTH PRODUCT 1.67 CFB FREQUENCY DEPENDANCE 1.68 SETTLING TIME 1.69 RISE TIME AND FALL TIME 1.70 PHASE MARGIN 1.70 CMRR (COMMON-MODE REJECTION RATIO) 1.71 PSRR (POWER SUPPLY REJECTION RATIO) 1.72 DIFFERENTIAL GAIN 1.73 DIFFERENTIAL PHASE 1.75 PHASE REVERSAL 1.75 CHANNEL SEPARATION 1.75 ABSOLUTE MAXIMUM RATING 1.76 REFERENCES 1.79 SECTION 1.3: HOW TO READ DATA SHEETS 1.83 THE FRONT PAGE 1.83 THE SPECIFICATION TABLES 1.83 THE ABSOLUTE MAXIMUMS 1.89 THE ORDERING GUIDE 1.92 THE GRAPHS 1.92 THE MAIN BODY 1.93 SECTION 1.4: CHOOSING AN OP AMP 1.95 STEP 1: DETERMINE THE PARAMETERS 1.96 STEP 2: SELECTING THE PART

Oscillator

Oscillator - Introduction - Resonance - Hartley Oscillator - Colpitts Oscillator - RC Oscillator

Voltage Regulator

Voltage Regulation Basic Linear Series Regulation Basic Linear Shunt Regulation Introduction to Switching Regulators